In device fabrication, insulating, semiconducting, and conducting layers are formed on a substrate. The layers are patterned to create features and spaces. The minimum dimension or feature size (F) of the features and spaces depends on the resolution capability of the lithographic systems. The features and spaces are patterned so as to form devices, such as transistors, capacitors, and resistors. These devices are then interconnected to achieve a desired electrical function, creating an integrated circuit (IC).
As the features and spaces decrease due to smaller and smaller F, it has become more difficult to fill the smaller gaps between the features with, for example, dielectric material. To enhance gapfill, doped silicate glass such as borophosphosilicate glass (BPSG) has been used. Doped silicate glass is effective in filling gaps due to its relatively low melting point, which allows it to be reflowed after being deposited.
Conventionally, BPSG is formed by various chemical vapor deposition (CVD) techniques. The BPSG is deposited at a relatively low temperature of about 400.degree. C. After deposition, the substrate is heated to at a high enough temperature to cause the glass to soften and flow. For example, annealing the BPSG at a temperature of 800.degree. C. causes the glass to flow and fill the gaps between the features.
Typically, different regions of the IC have different pattern factors, creating a complex topography on the surface of the substrate of device layer. Pattern factor is defined as the ratio of patterned and unpatterned areas. For example, in the array region of the dynamic random access memory (DRAM) IC, the patterned density is relatively high compared to that of the support or logic regions. As such, the spaces between the features are narrower in the array region versus those in the support or logic region. The doped silicate glass, although fills the gaps, is relatively conformal. That is, the topography of the underlying substrate or device layer is replicated in the deposited doped silicate glass.
After deposition, the doped silicate glass is polished by, for example, chemical mechanical polish (CMP) to provide a planar surface. A highly planarized surface topography is desirable since it allows for the deposition of additional integrated circuit components and permits greater device density. However, the complex topography creates difficulty in achieving a planar surface with CMP. In particular, dishing of the doped silicate glass occurs in wide spaces. Such dishing adversely impacts surface planarity, decreasing the depth of focus of subsequent lithographic processes.
From the above discussion, achieving gapfill of device structures with reduced dishing during CMP is desired.